The present invention relates to an internal voltage generator; more particularly, to an internal voltage generator for generating an internal voltage in response to a change in a temperature.
As a semiconductor memory device has been required to operate at a high speed with a low power voltage, and the semiconductor memory device has been manufactured to be highly integrated, an internal voltage generator has been used inside a dynamic random access memory (DRAM). In order to generate an internal voltage, a reference voltage is generated firstly. Then, the internal voltage is generated based on the reference voltage by using a charge pumping method or a down converting method.
A boosted voltage VPP and a back bias voltage VBB are examples of internal voltages generated by the charge pumping method. On the other hand, a core voltage VCORE is often one of the internal voltages generated by the down converting method.
Generally, the boosted voltage VPP, which is higher than an external supply voltage VDD, is supplied to a gate of a cell transistor in order to prevent cell data from being lost. For the same purpose, the back bias voltage VBB, which is lower than an external ground voltage VSS, is supplied to a bulk of the cell transistor. The core voltage VCORE is generated to maintain a constant voltage level even with fluctuations of the external supply voltage VDD. Therefore, power consumption is reduced and core operation becomes stabilized. The core voltage VCORE, which has a lower level than the level of the external supply voltage VDD, is generated by an amplifier for down converting the external supply voltage VDD. In order to generate the internal voltage, detecting the present level of the internal voltage is required before the charge pumping method or the down converting method.
FIG. 1 illustrates a block diagram showing a conventional back bias voltage generator. The back bias voltage generator includes a back bias voltage detecting unit 10 and a back bias voltage pumping unit 20.
The back bias voltage detecting unit 10 receives a back bias voltage VBB, i.e., an output of the back bias voltage pumping unit 20, and outputs a pumping control signal BBEb to control the driving of the back bias voltage pumping unit 20. The back bias voltage pumping unit 20 includes an oscillator, a pump controller, and a pump, for generating the back bias voltage VBB in response to the pumping control signal BBEb.
After the external supply voltage VDD is supplied to the DRAM and reaches a predetermined level for the DRAM to operate, a power up signal is activated. When the power up signal is activated, the DRAM begins to generate an internal voltage by using the charge pumping method. Before this point, the level of the back bias voltage VBB is at the ground voltage level. The back bias voltage detecting unit 10 senses that the back bias voltage VBB is lower than the core voltage VCORE and activates the pumping control signal BBEb. The back bias voltage pumping unit 20 is controlled by the pumping control signal BBEb.
FIG. 2 illustrates a schematic circuit diagram showing the back bias voltage detecting unit 10 depicted in FIG. 1. The back bias voltage detecting unit 10 includes a detector 12, a driver 14 and a level shifter 16.
The detector 12 detects the back bias voltage VBB, which is constant without respect to change in a temperature. The driver 14 drives its output as the core voltage VCORE or the ground voltage VSS in response to an output of the detector 12. The level shifter shifts the level of the output of the driver 14 to the level of the supply voltage VDD or the ground voltage VSS.
The detector 12 includes two PMOS transistors. The first PMOS transistor P1 whose drain and source are respectively coupled to a detecting node DET_NODE and the core voltage VCORE receives the ground voltage VSS through a gate. A bulk of the first PMOS transistor P1 is coupled to the core voltage VCORE. The second PMOS transistor P2 whose drain and source are respectively coupled to the ground voltage VSS and the detecting node DET_NODE receives the back bias voltage VBB through a gate. A bulk of the second PMOS transistor P2 is coupled to the core voltage VCORE.
As the back bias voltage VBB changes, a resistance value of the second PMOS transistor P2 changes. The difference in the resistance values between the first and second transistors P1 and P2 is used to detect the level of the back bias voltage VBB. For example, when the back bias voltage VBB decreases, the resistance value of the second PMOS transistor P2 increases. A voltage level of the detecting node DET_NODE becomes higher than the level of a threshold voltage, i.e., a switching point of the driver 14. Generally, the threshold voltage is a half level of the core voltage VCORE. Therefore, a lower transistor of the driver 14 is turned on and the ground voltage VSS is outputted to a driving node D_NODE.
When the ground voltage VSS is output to the driving node D_NODE, there is no level shifting operation in the level shifter 16. The pumping control signal BBEb is activated in a low logic level and drives the back bias voltage pumping unit 20.
Otherwise, when the back bias voltage VBB increases, the resistance value of the second PMOS transistor P2 decreases. The voltage level of the detecting node DET_NODE becomes lower than the level of the threshold voltage. The core voltage VCORE is output to the driving node D_NODE. When the core voltage VCORE is output to the driving node D_NODE, the level shifter 16 shifts the voltage level of the driving node D_NODE to the level of the supply voltage VDD. The pumping control signal BBEb activated in a high logic level does not drive the back bias voltage pumping unit 20. The back bias voltage VBB is maintained as a constant voltage level according to the operation of the back bias voltage pumping unit 20.
However, the conventional back bias voltage detecting unit 10 is not able to precisely detect the back bias voltage VBB in response to changes in a temperature. Though the back bias voltage VBB changes due to temperature changes, the back bias voltage detecting unit 10 will detect a constant voltage level.
Because voltages Vbs, Vgs and Vds required to operate the first and second PMOS transistors P1 and P2 hardly change within an operation range of the transistors and the first and second PMOS transistors P1 and P2 have similar resistance characteristics for change in the temperature, the back bias voltage detecting unit 10 will detect a constant voltage level without respect to changes in the temperature. Herein, the voltages Vbs, Vgs and Vds are voltages loaded between source and bulk, between gate and source and between drain and source of a transistor, respectively.